Tuesday, 23 February 2016

Easier UVM: Helping FPGA Designers


Learning and using UVM can seem like a daunting challenge, particularly if you are an FPGA Designer with limited time to dedicate to verification.

In this webinar you will be introduce to Easier™ UVM Coding Guidelines and Code Generator from Doulos. It includes examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™.



John AynsleyThe webinar, presented by Doulos CTO John Aynsley, consists of a one-hour session. Attendance is free of charge.




Beginning on Wednesday, 24th February, 2016 at 11:00am (CET).

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